AMD's Zen 6 processor family gives its standard and dense cores more distinct performance roles while preserving a common target for software optimization, according to chief architect Mike Clark. In a technical interview at AMD In-Depth, Clark described Zen 6 as the company's high-frequency design and Zen 6c as a denser core tuned to deliver the family's strongest instructions-per-clock performance.
The approach extends a two-core strategy AMD has developed since Zen 4. Earlier dense variants mainly used compact process technology to save area. For Zen 6c, AMD used the different frequency target to enlarge several internal queues and increase throughput without creating a separate programming model. Clark said the two versions are intended to have the same general behavior, allowing the same software optimizations to apply to both.
Zen 6c also receives the full last-level cache allocation. Clark described a configuration with 32 cores, 4 MB of L3 cache per core and 128 MB in total. Its floating-point scheduler is larger, and other queues have additional capacity intended to extract more work per clock and make better use of simultaneous multithreading. The conventional Zen 6 core, by contrast, is designed to reach a higher maximum frequency.
Both cores build on the dual-decode front end introduced with Zen 5. AMD focused on coordinating instruction delivery when a single thread spans the instruction cache and operation cache, an arrangement that can complicate timing and waste power. Clark said the Zen 6 work improves delivery efficiency while reducing unnecessary energy use.
The execution engine also reflects selective tradeoffs. AMD returned from three integer multiply units in Zen 5 to two in Zen 6 after finding limited benefit from the third unit. Moving back to distributed schedulers made the extra multiplier less attractive in area and scheduling complexity. At the same time, AMD added two vector neural-network-instruction pipelines as inference workloads became more important. Clark characterized that addition as a late change made after the overall floor plan had largely been set.
Other changes aim to use existing data paths more fully. Zen 6 can perform four 256-bit vector loads, taking advantage of wiring that already supported two 512-bit loads. AMD also addressed contention in the L2 cache, where prefetch traffic could consume bandwidth needed by demand requests. Clark said the revised design can sustain prefetch activity while delivering the intended 64 bytes per cycle for reads.
The design choices show AMD balancing frequency, density, cache capacity and per-clock throughput rather than treating Zen 6c as only a smaller copy. The common architecture remains important for developers, while the underlying implementations can be tailored to different server and computing workloads.
